// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    :  
// Module name  :  
// Full name    :  
// Time         : 2021 
// Author       : Haoxiaofei 
// Email        : 1531804419@qq.com
// Data         : 
// Version      : V 1.0 
// 
// Abstract     :
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 
// 
//
// *****************************************************************

//*******************
//DEFINE MODULE PORT
//*******************
module ME5(
    input wire rst_n,
    input wire clk,
    

    //ME与CPU接口
    input wire[10:0]  ram_addr,
    // input wire[15:0]  ram_addr,
    input wire[31:0]  ram_data,
    input wire        cpu_wen,
    input wire        cpu_ren,
    output wire[31:0] read_data_cpu,
    output wire me_array_bv5_dpram_valid,

    input  wire [4:0]me_array_action5_dpram_addr       ,
    // input  wire [15:0]me_array_action5_dpram_addr       ,
    input  wire       me_array_action5_dpram_wen        ,
    input  wire [31:0]me_array_action5_dpram_wdata      ,
    input  wire       me_array_action5_dpram_ren        ,
    output wire [31:0]me_array_action5_dpram_rdata      ,
    output wire me_array_action5_dpram_valid,
    //字段选择接口
    input  wire [0:1023]pktheader_vector,
    input  wire [255:0]ctr_field,
    input wire vector_rdy,//字段选择使能

//包头操作指令输出
    output wire action_en_o,
    output wire [3:0] action_o
    ); 

//*******************
//DEFINE LOCAL PARAMETER
//*******************
//parameter(s)

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
reg lookup_done_ff;
reg[31:0] match_res_t5;
reg lookup_done;
reg [31:0] match_res5_ff;
//WIRES
wire[31:0] match_res5; 


wire lookup_done5;
//wire lookup_success5;

wire select_end_o;

//ME5
wire [255:0]rule_in5;
//*********************
//INSTANTCE MODULE
//*********************
field_mux_256 U_5(
    .clk(clk),
    .rst_n(rst_n),
    .vector_rdy(vector_rdy),
    .ctr_field(ctr_field),
    .pktheader_vector(pktheader_vector),
    .select_end_o(select_end_o),
    .match_field(rule_in5)
    );

bv5_256 U_5_bv256(
    .clk(clk),
    .rst_n(rst_n),
    .lookup_en(select_end_o),

    .ram_addr(ram_addr),
    .ram_data(ram_data),
    .cpu_wen(cpu_wen),
    .cpu_ren(cpu_ren),
    .read_data_cpu(read_data_cpu),
    .me_array_bv5_dpram_valid(me_array_bv5_dpram_valid),

    .rule_in1(rule_in5),
    .match_res1(match_res5),
    .lookup_done1(lookup_done5)
    //.lookup_success1(lookup_success5)
    );

match2action_pkt_4 U_table5(
     .clk(clk),
    .rst_n(rst_n),
    .match_en(lookup_done),
    .match_res(match_res_t5),//match_res_t5
    .action_o(action_o),
    .action_en_o(action_en_o),

    .cpu_wen (me_array_action5_dpram_wen),
    .cpu_ren (me_array_action5_dpram_ren),
    .ram_data(me_array_action5_dpram_wdata),
    .ram_addr(me_array_action5_dpram_addr), 
    .read_data_valid(me_array_action5_dpram_valid),  
    .read_data_cpu(me_array_action5_dpram_rdata)
    );
//*********************
//MAIN CORE
//********************* 
always@(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    match_res5_ff <= 0;
  else 
    match_res5_ff <= match_res5;
end

always@(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    lookup_done_ff  <= 0;
  else if(lookup_done5)
    lookup_done_ff  <= 1;
  else 
    lookup_done_ff  <= 0;
end

always@(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    match_res_t5 <= 0;
  else if(lookup_done_ff)
    match_res_t5 <= match_res5_ff;
  else 
    match_res_t5 <= match_res_t5;
end

always@(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    lookup_done <= 0;
  else 
    lookup_done <= lookup_done_ff;
end

//*********************
endmodule    // hookup byte controller block
